The present invention relates generally to synchronous circuit design, and more particularly, to a circuit for measuring and compensating for variations in the process, voltage and temperature (PVT) conditions of an integrated circuit.
In digital circuits, synchronous logic elements operate by accepting and locking into a data signal during a transition of a clock signal. Such logic elements include D flip-flops, latch circuits, linear feedback shift registers (LFSRs), and counters. In order for a synchronous logic element to lock into a data signal, the signal must remain stable for some time prior to the clock edge, i.e., during a setup time. Also, the data signal usually must remain stable for some time after the clock edge, i.e., during a hold time, to be locked in by the synchronous logic element. If the data signal is not stable for both the setup time and the hold time of a synchronous logic element, the data signal may or may not be captured by the logic element.
FIG. 1A illustrates the operation of a synchronous logic element, specifically a D flip-flop DFF. In this example, the input data signal A is also used as the clock signal. Typically, the data signal and the clock signal are not shared, but instead are distinct signals. They are shown as sharing the same signal in FIGS. 1A and 1B to simplify the description of the related art. All descriptions herein apply to the case where the clock and data signals are distinct.
As shown in the timing diagrams of FIG. 1A, signal A is applied at the D input and clock input CK of the D flip-flop DFF. Therefore, the required setup time Tsu of the flip-flop DFF cannot be satisfied, and the Q output is indeterminate. This situation is shown in the timing diagram of FIG. 1A. However, such violations of setup time are not limited to instances where the input data signal is used to clock itself in a synchronous logic element.
For instance, clock skew (i.e., minor variations in the time at which clock signals arrive at their destinations in a chip) may cause the clock signal to arrive earlier than expected. Therefore, clock skew may cause a data signal to violate the setup time. Clock skew can be caused by, among other things, the process, voltage, and temperature (PVT) conditions of the synchronous logic element.
One way to prevent setup time violations is to add a delay element to the path of the clock signal. FIG. 1B shows a delay element added to the clock path of the D flip-flop DFF in FIG. 1A. As shown in the timing diagram of FIG. 1B, the delay element delays the signal A applied to the CK input by a time Td, thereby shifting the clock edge such that the data signal is stable during the setup time Tsu.
However, the delay time Td may vary according to the PVT conditions of the delay element. For example, if the temperature varies between from about xe2x88x9240xc2x0C. to 125xc2x0 C., the supply voltage varies by +/xe2x88x9215%, and/or the process conditions of the delay element varies between worst case fast and worst case slow, the delay time Td may vary from below 50% to over 100% of the designated delay time Td. Such changes in delay time Td may result in a violation of the setup time or the hold time of the D flip-flop DFF, or other types of synchronous logic elements.
One solution to this problem has been to use a type of variable delay element consisting of several small delay cells, where each small delay cell has a relatively short delay time Ts. The number of small delay cells within the variable delay element that are effectively used to delay the clock signal can be changed, based on PVT conditions. Accordingly, the delay time Td of the variable delay element (the sum total of delay times Ts of the effective small delay cells) of the effective can be kept constant, despite variances in PVT conditions. The tapped delay circuit 10, illustrated in FIG. 2, is an example of such a variable delay circuit.
As shown in FIG. 2, a tapped delay circuit 10 is comprised of a group of tapped small delay cells SD1, . . . , SD8, which are connected in series. The DELC1V15 delay component is an exemplary type of small delay cell SDn (n being within the range of 1 to 8 in FIG. 2) that can be used in tapped delay circuit 10. The DELC1V15 component has an expected delay time in worst case fast conditions of about 0.4 nanoseconds (ns), and an expected delay time during worst case slow conditions of about 1.0 ns. However, for the tapped delay circuit 10 and other subsequently described circuits, any component having a known delay time Ts may be used instead of the DELC1V15 component. The desired resolution and the frequency of the input clock, CLK, generally determine the selection of the delay component.
As discussed above, each small delay cell SDn in FIG. 2 has a relatively short time delay time Ts. An input signal IN is input to the first small delay cell, and the delayed signal propagates from small delay cell SD1 to the next small delay cell SD2 to the next small delay cell SD3, etc., until it propagates to the last small delay cell SD8. Therefore, the signal at tap 1 will be delayed by Ts, the signal at tap 2 will be delayed by 2*Ts, and so forth. Multiplexor MUXA selects and outputs the tap signal based corresponding to a series number received via control signal CTL.
FIG. 3 illustrates a variable delay control circuit 100, in which the delay time Td of tapped delay circuit 10 of FIG. 2 is controlled by shift register array 30 and phase detector 40, through adjustment of the series number. The number of small delay cells SDn in tapped delay circuit 10 is based on the desired resolution of variable delay control circuit 100.
The shift register array 30 contains the series number, which comprises a number of bits that corresponds to the number of small delay cells SDn. If the tapped delay circuit 10 has eight small delay cells SDn, as illustrated in FIG. 2, the shift register array 30 will hold a series number comprising eight digits. Each digit corresponds to a specific small delay cell tap. One of the digits contains a xe2x80x9c1xe2x80x9d bit while all of the other digits contain xe2x80x9c0xe2x80x9d bits. The digit containing the xe2x80x9c1xe2x80x9d bit corresponds to the tap whose signal is selected and output by multiplexor MUX A.
The variable delay control circuit 100 operates as follows. First, an input clock signal CLK is input to the first tapped delay circuit 10 of the tapped delay circuit 10. The tapped delay circuit 10 outputs a clock signal P_CK delayed according to delay time Td, which is determined by the series number in shift register array 30. Both the delayed clock signal P_CK and the input clock signal CLK are sent to phase detector 40, which detects a phase difference between the input clock CLK and the delayed clock signal P_CK.
Based on a detected phase difference, phase detector 40 will generate either a right shift signal CSR or a left shift signal CSL, if necessary, which shifts the xe2x80x9c1xe2x80x9d bit of the series number in the shift register array 30 to either the left or right. As a result of the modified series number, the multiplexor MUX A of the tapped delay circuit 10 will select and output a different tap signal.
The variable delay control circuit 100 of FIG. 3 can be considered a type of delay-locked loop (DLL), because it synchronizes or aligns the delayed clock signal PCK13 CK with the input clock signal CLK.
FIG. 4 illustrates a timing diagram including reference signals P_d0 and P_d1 of phase detector 40, which are generated based on clock signal CLK. Specifically, the phases of P_d0 and P_d1 define the boundaries of an optimally delayed clock signal. In other words, if the time delay Td of the tapped delay circuit 10 is within circuit design requirements (e.g., meet required setup and hold times), the phase of P_CK will fall between the phases of P_d0 and P_d1. Therefore, phase detector 40 compares the phase of P_CK signal to P_d0 and P_d1 to determine whether adjustments to the series number and parallel number are necessary.
Specifically, phase detector 40 checks whether the rising edge of signal P_CK falls between the rising edges of signals P_d0 and P_d1, i.e., falls within time window Tw. If the edge of P_CK does not fall within window Tw, then phase detector will generate CSR or CSL signals to modify the series number, thereby causing the phase of P_CK to shift to the left or right. For instance, if the rising edge of P_CK falls within time interval R1 of FIG. 4, where both P_d0 and P_d1 are high, phase detector 40 will generate a right shift signal CSR that causes the series number to decrease (i.e., cause the xe2x80x9c1xe2x80x9d bit to shift to the right), thereby causing P_CK to shift toward the left. Alternatively, if the rising edge of P_CK falls within time interval L1, where both P_d0 and P_d1 are low, the phase detector 40 will generate a left shift signal CSL that causes the series number to increase (i.e., cause the xe2x80x9c1xe2x80x9d bit to shift to the left), thereby shifting P_CK toward the right.
Once the rising edge of P_CK falls within window Tw, then the variable delay control circuit 100 determines that the delay time Td of the tapped delay circuit 10 is correct. However, a problem may arise within variable delay control circuit 100, which causes delay time Td to be set improperly set.
Specifically, when the system is powered on, the series number may be preset to a number that causes P_CK to be ahead of input clock signal CLK by a half cycle, or preset to a number that causes P_CK to be delayed by a full cycle with respect to CLK. Such a problem is caused variations in PVT conditions and may result in the delay times of each small delay cell SDn of the tapped delay circuit 10 to change from below xe2x88x9250% to above 100% of the normal delay time.
As a result of this problem, the edge of signal P_CK may fall within one of the time intervals L2 or R2 of the timing diagram in FIG. 4. If the rising edge falls in L2, the phase detector 40 will generate a right shift signal CSR causing the rising edge of P_CK to fall within the time window Tw of interval HC (half a cycle late). Otherwise, if the rising edge falls in R2, phase detector 40 will generate a left shift signal CSL causing P_CK rising edge to fall within FC (a full cycle late).
Alternatively, the above problem may cause the edge of signal P_CK to fall within one of time intervals HC or FC. In this situation, the coarse phase detector 40 will not generate any right shift CSR or left shift signals CSL.
If the series number is set such that the rising edge of P_CK falls within either interval HC or FC, the delay time Td of variable delay circuit 20 will not be correctly set. Therefore, it would be advantageous to detect PVT conditions after the tapped delay circuit 10 is powered on, so that the series number of the shift register array can be correctly preset and the delay time of a variable delay circuit will meet the delay requirements (e.g., setup time and hold time of a synchronous logic unit).
Further, it would generally be advantageous in the related art to determine the effects of various PVT conditions on an integrated circuit for the purposes of programming the delay components of the chip or for designing circuits to compensate for the PVT conditions.
The present invention provides a delay compensation circuit, which measures PVT conditions of an integrated circuit by measuring the operating conditions of components inside the integrated circuit. In particular, the delay compensation circuit outputs digital signals representative of the PVT conditions, which depend on the effective delay time of delay components within the chip. Updated PVT information can be obtained periodically from the delay compensation circuit during and used to control variable delay circuits within the chip. Also, such information can be collected and used to determine the range of PVT conditions that a chip must operate under in a specific system or application. This information can be quite useful for designing chips that meet certain performance criteria, regardless of variations in PVT conditions.
In an exemplary embodiment of the present invention, the delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from a delay component within a tapped delay circuit. Therefore, the clock signal of each sampler module is delayed by a greater amount than the previous sampler module. When a fixed input signal is applied to each sampler module, the number of sampler modules that lock into the input signal is detected and converted into a value representative of the current PVT conditions.
Another exemplary embodiment of the present invention provides an improved variable delay control circuit that uses information obtained by the delay compensation circuit to control the delay time of the variable delay component to meet the setup and hold time requirements of a chip component despite variations in PVT conditions.
In another exemplary embodiment, the variable delay control circuit includes a variable delay component, which is a tapped delay circuit. The delay compensation circuit periodically measures the PVT conditions of the chip. The digitized output signals are encoded into a series number, which is transmitted from the shift register array to a multiplexor of the tapped delay circuit.
A variable delay control circuit utilizing the delay compensation circuit of the present invention can be used with a plurality of digital chips having setup and hold time requirements. Such chips may include input and output buffers, field programmable gate arrays (FPGAs), delay-locked loops (DLLs), digital phase-locked loops (PLLs), D flip-flops, and other types of synchronous logic elements. In addition, the PVT information provided by the delay compensation circuit of the present invention can be used for designing such chips to be used in timing critical applications.
In another exemplary embodiment of the present invention, a variation circuit stores the maximum and minimum values output by the delay compensation circuit. Such information can be used to determine the range of PVT operating conditions for a particular application, or to ensure that a chip is not operating outside of this range.
Advantages of the present invention will become more apparent from the detailed description given hereafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modification within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.